As is well known, an inverter circuit converts a direct current (DC) voltage to an alternating current (AC) voltage and supplies the AC voltage to an inductive load (i.e., inductance L) such as an inductive motor. For example, this type of inverter circuit is constructed with a semiconductor device 100 shown in FIG. 23A. The semiconductor device 100 includes an insulated-gate bipolar transistor (IGBT) 100i and an antiparallel diode 100d that is connected in antiparallel with the IGBT 100i. 
An inverter circuit for generating a three-phase AC voltage is constructed with six semiconductor devices 100. As shown in FIG. 23B, each phase is generated using two semiconductor devices 100 connected in series between a DC power source and a ground potential. The IGBT 100i serves as a switching element. The antiparallel diode 100d serves as a free wheel diode. A load current flowing through an inductance (not shown) coupled to an output can flow through the diode 100d, when the IGBT 100i is turned off. Thus, a sudden change in the load current can be prevented. Such a diode 100d is called a flee wheel diode (FWD).
The semiconductor device 100 can be implemented such that the IGBT 100i and the diode 100d are formed in separate semiconductor substrates (chips). However, to reduce size of the semiconductor device 100, it is preferable that the IGBT 100i and the diode 100d be formed in the same semiconductor substrate
FIG. 24 illustrates a semiconductor device 91 disclosed in U.S. Pat. No. 7,154,145 corresponding to JP-A-2005-101514. In the semiconductor device 91, an IGBT and an antiparallel diode are formed in the same semiconductor substrate. Specifically, a p-type base layer (well) 2 is formed on a first side of an N−-type semiconductor substrate 1 for each IGBT cell. An N+-type cathode layer 4 and a P+-type collector layer 5 are formed on a second side of the semiconductor substrate 1 and located just below the base layer 2. The p-type base layer 2 of each IGBT cell includes first and second side diffusion regions 2SDR1, 2SDR2 and a flat region 2FR located between the first and second side diffusion regions 2SDR1, 2SDR2. The flat region 2FR has an emitter region 3 and a bottom surface penetrated by an insulated gate trench 6. The first side diffusion region 2SDR1 is located just above the N+-type cathode layer 4. The N+-type cathode layer 4 is located adjacent to the P+-type collector layer 5. A diode cell is constructed with the N−-type semiconductor substrate 1, the p-type base layer 2, and the N+-type cathode layer 4. An emitter electrode 10 of the IGBT cell is integrated with an anode electrode of the diode cell, and a collector electrode 11 of the IGBT cell is integrated with a cathode electrode of the diode cell. Thus, the diode cell is connected in antiparallel with the IGBT cell.
The IGBT cell in the semiconductor device 91 is a trench gate IGBT. In a trench gate IGBT, channels are formed at both sides of an insulated gate trench so that channel density can be increased. Therefore, a trench gate IGBT can have a low on-voltage compared to a planar gate IGBT.
FIG. 25 illustrates a trench gate IGBT 92 disclosed in U.S. Pat. No. 6,737,705 corresponding to JP-A-2001-308327. The IGBT 92 is designed to achieve, not only a low on-voltage, but also a low switching loss, thereby reducing total loss. As shown in FIG. 25, the IGBT 92 includes a silicon substrate 21, a lightly doped N-type drift layer 22, a P-type base layer 23, an N+-type source region 24, a gate oxide film 25 arranged in a trench penetrating through the p-type base layer 23, a gate electrode 26 arranged in the trench through the gate oxide film 25, an interlayer insulation film 27, an emitter electrode 28 coupled to the N+-type source region 24, and a collector electrode 29 coupled to an opposite surface of the silicon substrate 21. The p-type base layer 23 is divided by the trench into a body region 23a and a floating region 23b. The body region 23a is coupled to the emitter electrode 28 and has the N+-type source region 24 located adjacent to the trench. Therefore, the body region 23a serves as a channel region. The floating region 23b is not coupled to the emitter electrode 28 and does not have the N+-type source region 24. The floating region 23b serves as a carrier storing region for storing carriers.
As described above, the IGBT 92i has a structure in which the channel regions (i.e., body regions 23a) are spaced from each other by the carrier storing region (i.e., floating region 23b). Therefore, an IGBT like the IGBT 92i is hereinafter called “spaced-channel IGBT”. According to U.S. Pat. No. 6,737,705, when the ratio of the width of the body region 23a to the width of the floating region 23b is from 1:2 to 1:7, the IGBT 92i has both a low on-voltage and a low switching loss so that total loss can be reduced.
When a spaced-channel IGBT like the IGBT 92i is applied to a semiconductor device for an inverter circuit, it is preferable that the spaced-channel IGBT and an antiparallel diode be formed in the same semiconductor substrate. In such an approach, like the semiconductor device 91 shown in FIG. 24, the semiconductor device size can be reduced. However, when the spaced-channel IGBT and an antiparallel diode are formed in the same semiconductor substrate, there may be mutual interference between the spaced-channel IGBT and the antiparallel diode.